AMD-766 Datasheet, PDF (82/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
PM[D3:C0]: General-Purpose IO Pins GPIO[19:0] Select Registers
PM[FF:F4]: General-Purpose IO Pins GPIO[31:20] Select Registers
IO mapped (base pointer: C3A58); offset: D3-C0h and F5-F4h (one single-byte register for each GPIO pin).
Default: see the MODE field definition.
See section 4.6.5 for details about GPIO hardware.
Usage note: to set a GPIO pin as a software-controlled output, its corresponding GPIO register should be written
with the value 04h for a low and the value 05h for a high.
7
6
5
4
3:2
1
0
Reserved LTCH_STS RTIN
DEBOUNCE MODE[1:0]
X1
X0
X[1:0]. Read-write. Extra select bits. These bits have meaning for GPIO pin inputs and outputs and to control the
input paths to some alternative functions on these pins. This field is encoded as follows based on if the pin is
programmed as an input or output.
IO (MODE) Bit
Input
X0
Name
ACTIVEHI
Function
0=The pin is active low and the signal is inverted as it is brought into the
input path. 1=The pin is active high and therefore not inverted as it is
brought through the input path.
Input
X1
LATCH 0=The latched version of the signal is not selected. 1=The latch output is
selected.
Output
X[1:0]=0h
Output is forced low.
Output
X[1:0]=1h
Output is forced high.
Output
X[1:0]=2h
GPIO output clock 0 (specified by PMDC[15:0]).
Output
X[1:0]=3h
GPIO output clock 1 (specified by PMDC[31:16]).
MODE[1:0]. Pin mode select. Read-write. These specify the GPIO pin modes as follows:
MODE[1:0] GPIO pin mode
00b
General purpose input
01b
General purpose output
1xb
Pin specified to perform alternate function (non-GPIO mode). For GPIO[13, 16],
MODE[0] selects between two alternate functions. For GPIO[31:24, 17, 9, 2], no
alternate function exists, so this mode is not valid.
DEBOUNCE. Debounce the input signal. Read-write. 1=The input signal is required to be held active without
glitches for 12 to 16 milliseconds before being allowed to set the GPIO latch or being capable of being passed along
to the circuitry being controlled by the output of the input path.
RTIN. Real time in. Read only. This provides the current, not-inverted state of the pad for the pin that corresponds
to the register.
LTCH_STS. GPIO latch status. Read; set by hardware; write 1 to clear. This provides the current state of the latch
associated with the input path for the pin that corresponds to the register. This may be cleared by writing a 1 to this
location or through PMD4.
The table below shows the default states for the GPIO registers and the pin definitions base on the state of
MODE[1:0]. The “Default” column shows the defaults for all the bits in the register. The “Mode” field shows the
value required in order to enable the function specified in the “Signal Name” column (“x” specifies that the bit does
not matter). The “Input Path” field shows how the alternate function signal is mapped into internal logic; “GPIO”
specifies that the signal passes through the GPIO input path (and may therefore use the polarity, latch, and debounce
controls from the GPIO circuit); “Direct” specifies that the signal comes directly from the pad; “NA” specifies that it
is an output signal.
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