AMD-766 Datasheet, PDF (49/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
RTC71: Real-Time Clock Legacy Data Port.
IO mapped (fixed); offset: 0071h. Read-write.
7:0
RTCDATA
RTCDATA. Real time clock data. This is the data port for accesses to the real-time clock CMOS RAM that is
indexed by RTC70.
RTC72 and RTC73: Real-Time Clock 256-Byte Address and Data Port.
IO mapped (fixed); offsets: 0072h and 0073h. Read-write.
These two 8-bit ports are similar to RTC70 and RTC71. However, RTC72, the address register, provides the full
eight bits needed to access all 256 bytes of CMOS RAM. RTC73, the data port, provides access to the CMOS data
indexed by RTC72. See RTC70 for details about reading RTC72.
Real-Time Clock Alarm And Century Registers.
RTC indexed address space (indexed by RTC70); offsets: 7Dh, 7Eh, and 7Fh. Attribute: read-write. The day alarm,
month alarm, and centenary value are stored in CMOS RAM indexed address space.
CMOS RAM offset Function
Range for binary mode Range for BCD mode
7Dh
Date alarm
01-1Fh
01-31h
7Eh
Month alarm
01-0Ch
01-12h
7Fh
Century field
13-63h
19-99h
Bits[7:6] of the date alarm (offset 7Dh) are reserved; writes to them have no effect and they always read back as zero.
To place the RTC into 24-hour alarm mode, an invalid code must be written to bits[5:0] of the date alarm byte
(anything other than 01h to 31h for BCD mode or 01h to F1h for hex mode). Refer to the ACPI specification for
specifics on the month alarm field (offset 7Eh) and century field (offset 7Fh) functionality.
5.4 Enhanced IDE Controller Configuration Registers (C1Axx)
These registers are in PCI configuration space, function 1. See section 5.1.2 for a description of the register naming
convention.
C1A00: EIDE Controller Vendor And Device ID
Configuration space; function 1; offset: 03-00h. C1A00 default: 7411 1022h. Read only.
31:16
15:0
DID
VID
VID. Vendor ID.
DID. EIDE controller device ID.
C1A04: EIDE Controller Status And Command Register
Configuration space; function 1; offset: 07-04h. Default: 0200 0000h.
31:16
15:0
STATUS[15:0]
COMMAND[15:0]
COMMAND[0] IO Space, IOEN. Read-write. 1=Enables access to the IO space for the EIDE controller.
COMMAND[1] Memory Space. Read only. This bit is fixed in the low state.
COMMAND[2] Bus Master Enable, BMEN. Read-write. 1=Enables EIDE bus master capability.
COMMAND[15:3]. Read only. These bits are fixed at their default values.
STATUS[11:0]. Read only. These bits are fixed at their default values.
STATUS[12] Received Target Abort, RTGTABT. Read; set by hardware; write 1 to clear. 1=The IC received a
target abort while the EIDE controller was master of the PCI bus.
STATUS[13] Received Master Abort, RMASABT. Read; set by hardware; write 1 to clear. 1=An EIDE master
cycle was terminated with a master abort.
STATUS[15:14]. Read only. These bits are fixed at their default values.
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