AMD-766 Datasheet, PDF (55/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
IBMA: Secondary Bus Master IDE Status Register
IO space (base pointers: C1A20); offset: 0Ah. Default: 00h.
7:0
SSTAT
SSTAT[0] Bus Master IDE Active, ACTV. Read only.
SSTAT[1] Error, ERR. Read; set by hardware; write 1 to clear.
PSTAT[2] Interrupt, IRQ. Read; set by hardware; write 1 to clear. This bit is set by the rising edge of the IDE
interrupt line.
SSTAT[4:3]. Reserved.
SSTAT[5] Drive 0 DMA Capable, DMA0C. Read-write.
SSTAT[6] Drive 1 DMA Capable, DMA1C. Read-write.
SSTAT[7] Simplex Only. Read only.
IBMC: Secondary Bus Master IDE PRD Table Address Register
IO space (base pointers: C1A20); offset: 0Ch. Default: 0000 0000h.
31:2
1:0
PPRDADD
Reserved
SPRDADD[1:0]. Read only. These bits are fixed in the low state
SPRDADD[31:2] Secondary physical region descriptor table base address, SRDADD. Read-write.
5.6 USB Host Controller Configuration Registers (C4Axx)
These registers are in PCI configuration space, function 4. See section 5.1.2 for a description of the register naming
convention.
C4A00: USB Controller Vendor And Device ID
Configuration space; function 4; offset: 03-00h. Default: 7414 1022h. Read only.
31:16
15:0
DID
VID
VID. Vendor ID.
DID. USB controller device ID.
C4A04: USB Controller Status And Command Register
Configuration space; function 4; offset: 07-04h. Default: 0280 0000h.
31:16
STATUS[15:0]
15:0
COMMAND[15:0]
COMMAND[0] IO Space Enable, IOEN. Read-write. 1=Enables access to the IO space for the keyboard/mouse
controller ports use in legacy emulation.
COMMAND[1] Memory Space Enable. Read-write. 1=Enables access to the memory space for the host controller
registers.
COMMAND[2] Bus Master Enable. Read-write. 1=Enables USB bus master capability.
COMMAND[4] Memory Write and Invalidate Enable. Read-write. 1=Enables bus master to issue memory write
and invalidate cycles.
COMMAND[8] SERR# Detection Enable. Read-write. This bit has no effect.
COMMAND[15:9,7:5,3]. Read only. These bits are fixed at their default values.
STATUS[11:0]. Read only. These bits are fixed at their default values.
STATUS[12] Received Target Abort. Read; set by hardware; write 1 to clear. 1=The IC received a target abort
while the USB controller was master of the PCI bus.
STATUS[13] Received Master Abort. Read; set by hardware; write 1 to clear. 1=A USB master cycle was
terminated with a master abort.
STATUS[15:14]. Read only. These bits are fixed at their default values.
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