AMD-766 Datasheet, PDF (85/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
occurs after the address match occurs and before the last acknowledge, then this bit is not set. This bit resides on the
VDD_AUX power plane.
HSLV_STS. Host-as-slave address match status. Read; set by hardware; write 1 to clear. 1=An SMBus master
(including the host controller) generated an SMBus write cycle with a 7-bit address that matched the one specified by
PMEE. This bit is not set until the end of the acknowledge bit after the last byte is transferred over the SMBus cycle;
if a time out occurs after the address match occurs and before last acknowledge, then this bit is not set. This bit
resides on the VDD_AUX power plane.
SMBA_STS. SMBALERT# interrupt status. Read; set by hardware; write 1 to clear. 1=SMBALERT# was
asserted. This bit may not be set unless the SMBALERT# function is selected by C3A46[10:9].
SMB_BSY. SMBus busy. Read only. 1=The SMBus is currently busy with a cycle generated by either the host or
another SMBus master.
PME2: SMBus Global Control Register
IO mapped (base pointer: C3A58); offset: E3-E2h. Default: 00h.
The _EN bits of this register work in conjunction with the _STS bits in PME0 to generate SCI or SMI interrupts
(based on the state of PM04[SCI_EN]).
15
14
13
12
11
10
9
8
Reserved Reserved Reserved Reserved Reserved SMBA_EN HSLV_EN SNP_EN
7
6
5
4
3
2:0
Reserved Reserved ABORT HCYC_EN HOSTST CYCTYPE
CYCTYPE. Host-generated SMBus cycle type. Read-write. This field specifies the type of SMBus cycle that is
generated when it is initiated by the HOSTST command. It is encoded as follows (for each of the registers, the slave
address is specified by PME4[7:1] and “receive” or “read” versus “send” or “write” is specified by PME4[0]):
CYCTYPE SMBus Cycle Type Registers
000b
Quick command Data bit in PME4[0]
001b
Receive or send byte Data in PME6[7:0]. If the address in PME4 is 0001_1001b and data received
is 111_0xxxb, then another byte is received in PME6[15:8]; see the
SMBALERT description in the system management section of this document.
010b
Read or write byte Command in PME8; data in PME6[7:0]
011b
Read or write word Command in PME8; data in PME6[15:0]
100b
Process call
Command in PME8; write data is placed in PME6[15:0]; then this data is
replaced with the read data in the second half of the command
101b
Read or write block Command in PME8; count data in PME6[5:0]; block data in the PME9 FIFO
11xb
Reserved
HOSTST. Host start command. Write 1 only. 1=The SMBus host logic initiates the SMBus cycle specified by
CYCTYPE. Writes to this field are ignored while PME0[HST_BSY] is active.
HCYC_EN. Enable host SMBus controller SMI or SCI interrupt. Read-write. 1=The SMBus host controller status
bits, PME0[TO_STS, HCYC_STS, PRERR_STS, COL_STS, ABRT_STS], are enabled to generate SMI or SCI
interrupts. 0=No interrupts are generated when these bits are set.
ABORT. Abort current host transfer command. Write 1 only. 1=The SMBus logic generates a stop event on the
SMBus pins as soon as possible. After the stop event completes, PME0[ABRT_STS] is set high.
SNP_EN. Snoop address match interrupt enable. Read-write. 1=Enables an SMI or SCI interrupt when
PME0[SNP_STS] is set. 0=No interrupts are generated when this bit is set. This bit resides on the VDD_AUX
power plane.
HSLV_EN. Host-as-slave address match interrupt enable. Read-write. 1=Enables an SMI or SCI interrupt when
PME0[HSLV_STS] is set. 0=No interrupts are generated when this bit is set. This bit resides on the VDD_AUX
power plane.
SMBA_EN. SMBALERT# interrupt enable. Read-write. 1=Enables an SMI or SCI interrupt when
PME0[SMBA_STS] is set. 0=No interrupts are generated when this bit is set. This bit has no effect unless the
SMBALERT# function is selected by C3A46[10:9].
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