AMD-766 Datasheet, PDF (8/96 Pages) Advanced Micro Devices – Peripheral Bus Controller

23167B – March 2001
Preliminary Information
AMD-766^TM Peripheral Bus Controller Data Sheet
3.2 PCI Interface
Pin name and description
AD[31:0]. Address-data bus.
CBE_L[3:0]. Command-byte enable bus.
DEVSEL#. Device select.
FRAME#. Frame signal.
IDSEL. Identification select signal.
IRDY#. Master ready signal.
PAR. Parity signal.
PCIRST#. PCI reset. This is the system reset signal for logic that is
powered by the system’s main power supplies.
PCLK. 33 MHz PCI clock. This is required to remain active during reset
and when the IC enters the power-on suspend state (POS).
PGNT#. Master grant signal.
PIRQ[A, B, C, D]#. PCI interrupt requests. Only PIRQD# is an output
as well as an input; it may be driven active by the USB interrupt. The
other three pins are inputs only.
PREQ#. Master request signal.
SERR#. PCI system error signal. This may be asserted by the system to
indicate a system error condition. If enabled by RTC70[7], an NMI
interrupt may be generated.
STOP#. Target abort signal.
TRDY#. Target ready signal.
IO cell
type
IO
IO
IO-PU
IO-PU
Input
IO-PU
Output
Output
Input
Input
IOD-
PU
Output
Input-
PU
IO-PU
IO-PU
Power
plane
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD_
SOFT
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
During
Reset
3-state
3-state
3-state
3-state
-
3-state
3-state
Low
-
-
-
High
-
3-state
3-state
Post
Reset
3-state
3-state
3-state
3-state
-
3-state
3-state
High
-
-
-
High
-
3-state
3-state
POS
3-state
3-state
3-state
3-state
-
3-state
3-state
High
-
-
-
High
-
3-state
3-state
3.3 Processor Interface
Pin name and description
IO cell
type
A20M#. Address bit[20] mask to the processor. This output is a logical OD
OR of the KA20G pin from the keyboard controller and PORT92[A20EN].
CPURST#. CPURST#. Reset to the processor. This is the reset to
OD
processor(s). See sections 4.1.1 and 4.6.1.5.1.
FERR#. Floating-point error from the processor. The processor asserts Input
this signal to indicate a floating-point error has occurred. This is used to w/H
create IRQ13 to the PIC and IOAPIC.
IGNNE#. Ignore numeric error to the processor.
OD
INIT#. Initialization interrupt to the processor.
OD
INTR. Interrupt request to the processor.
OD
NMI. Non-maskable interrupt request to the processor.
OD
PICCLK. Interrupt message bus clock for the IOAPIC. This is controlled IOD
through C0Ax4B[APICCKS]. During POS, PICCLK may be selected to
either be active or forced low by C3A50[APIC_POSEN].
PICD0# and PICD1#. Interrupt message bus data bits 1 and 0 for the
IOD
IOAPIC.
SMI#. System management interrupt to the processor.
OD
STPCLK#. Processor stop-grant request.
OD
WSC#. Write snoop complete. This signal is used to guarantee the most IOD
recent PCI bus writes from the IC to system memory are visible to the host.
See section 4.3.2 for more details. This signal requires an external pull-up
resistor with a value between 10K to 200K ohms.
Power
plane
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
During
Reset
3-state
Low
-
3-state
3-state
Low
Low
Func.
3-state
3-state
3-state
3-state
Post
Reset
3-state
Func.
-
3-state
3-state
Low
Low
Func.
3-state
3-state
3-state
3-state
POS
3-state
3-state
-
3-state
3-state
low
Low
3-state
3-state
Active
3-state
8