EP2SGX130GF1508C4 Datasheet, PDF (95/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Figure 2–60. DSP Block Interface to Interconnect
C4 Interconnect
Direct Link Interconnect
from Adjacent LAB
R4 Interconnect
Stratix II GX Architecture
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
LAB
36
18
36
DSP Block
Row Structure
LAB
16
16
12
Control
36
A[17..0]
OA[17..0]
36
B[17..0]
OB[17..0]
Row Interface
Block
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
f
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in Table 2–23.
Refer to the DSP Blocks in Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook for more information on DSP blocks.
Altera Corporation
October 2007
2–87
Stratix II GX Device Handbook, Volume 1