EP2SGX130GF1508C4 Datasheet, PDF (80/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

TriMatrix Memory
The RAM blocks in Stratix II GX devices have local interconnects to allow
ALMs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driven by the R4, C4, and direct link interconnects
from adjacent LABs. The M512 RAM blocks can communicate with LABs
on either the left or right side through these row interconnects or with
LAB columns on the left or right side with the column interconnects. The
M512 RAM block has up to 16 direct link input connections from the left
adjacent LABs and another 16 from the right adjacent LAB. M512 RAM
outputs can also connect to left and right LABs through direct link
interconnect. The M512 RAM block has equal opportunity for access and
performance to and from LABs on either its left or right side. Figure 2–50
shows the M512 RAM block to logic array interface.
Figure 2–50. M512 RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
Direct link
16
interconnect
to adjacent LAB
36
dataout
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
M4K RAM
Block
datain
control
signals
clocks
byte
enable
address
Direct link
interconnect
from adjacent LAB
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
2–72
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007