EP2SGX130GF1508C4 Datasheet, PDF (26/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Transceivers
Figure 2–16. Receiver PLL and CRU
÷1, 4, 5, 8, 10, 16, 20, or 25
÷m
rx_cruclk
÷N
÷1, 2, 4
rx_locktorefclk
rx_locktodata
rx_datain
rx_pll_locked
PFD
Up
÷2
Down
Up
Down
Clock Recovery Unit (CRU)
CP+LF
VCO
÷L
÷1, 2, 4
rx_freqlocked
rx_rlv[ ]
High Speed RCVD_CLK
Low Speed RCVD_CLK
The receiver PLLs and CRUs can support frequencies up to 6.375 Gbps.
The input clock frequency is limited to the full clock range of 50 to
622 MHz but only when using REFCLK0 or REFCLK1. An optional
RX_PLL_LOCKED port is available to indicate whether the PLL is locked
to the reference clock. The receiver PLL has a programmable loop
bandwidth which can be set to low, medium, or high. The Quartus II
software can statically set the loop bandwidth parameter.
All the parameters listed are programmable in the Quartus II software.
The receiver PLL has the following features:
■ Operates from 600 Mbps to 6.375 Gbps.
■ Uses a reference clock between 50 MHz and 622.08 MHz.
■ Programmable bandwidth settings: low, medium, and high.
■ Programmable rx_locktorefclk (forces the receiver PLL to lock
to the reference clock) and rx_locktodata (forces the receiver PLL
to lock to the data).
■ The voltage-controlled oscillator (VCO) operates at half rate and has
two modes. These modes are for low or high frequency operation
and provide optimized phase-noise performance.
■ Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and
25. Not all settings are supported for any particular frequency.
■ Two lock indication signals are provided. They are found in PFD
mode (lock-to-reference clock), and PD (lock-to-data).
2–18
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007