EP2SGX130GF1508C4 Datasheet, PDF (39/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–24 shows the data path in serial loopback mode.
Figure 2–24. Stratix II GX Block in Serial Loopback Mode with BIST and PRBS
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
Analog Receiver and
Transmitter Logic
FPGA
Logic
Array
TX Phase
Compensation
FIFO
BIST
Incremental
Verify
Byte
Serializer
RX Phase
Compen-
sation
FIFO
Byte
Ordering
8B/10B
20 ^Encoder
Byte
De-
serializer
8B/10B
Decoder
Rate
Match
FIFO
Serializer
BIST
PRBS
Verify
Deskew
FIFO
Word
Aligner
Serial
Loopback
De-
serializer
Clock
Recovery
Unit
Receiver Digital Logic
Parallel Loopback
The parallel loopback mode exercises the digital logic portion of the
transceiver data path. The analog portions are not used in this loopback
path, and the received high-speed serial data is not retimed. This protocol
is available as one of the sub-protocols under Basic mode and can be used
only for Basic double-width mode.
In this loopback mode, the data from the internally available BIST
generator is transmitted. The data is looped back after the end of PCS and
before the PMA. On the receive side, an internal BIST verifier checks for
errors. This loopback enables you to verify the PCS block.
Altera Corporation
October 2007
2–31
Stratix II GX Device Handbook, Volume 1