EP2SGX130GF1508C4 Datasheet, PDF (242/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Timing Model
Table 4–59. M512 Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Parameter
-3 Speed
Grade(2)
Min Max
t_M512RC
Synchronous
2089
read cycle time
t_M512WERESU
Write or read
22
enable setup
time before clock
t_M512WEREH
Write or read
203
enable hold time
after clock
t_M512DATASU
Data setup time 22
before clock
t_M512DATAH
Data hold time 203
after clock
t_M512WADDRSU Write address
22
setup time before
clock
t_M512WADDRH Write address
203
hold time after
clock
2318
t_M512RADDRSU
t_M512RADDRH
t_M512DATACO1
t_M512DATACO2
t_M512CLKL
t_M512CLKH
Read address
setup time before
clock
Read address
hold time after
clock
Clock-to-output
delay when using
output registers
Clock-to-output
delay without
output registers
Minimum clock
low time
Minimum clock
high time
22
203
298
2102
1315
1315
478
2345
-3 Speed Grade
(3)
-4 Speed Grade
-5 Speed Grade
Unit
Min Max Min Max Min Max
2089 2433 2089 2587 2089 3104 ps
23
24
29
ps
213
226
272
ps
23
24
29
ps
213
226
272
ps
23
24
29
ps
213
226
272
ps
23
24
29
ps
213
226
272
ps
298 501 298 533 298 640
ps
2102 2461 2102 2616 2102 3141 ps
1380
1468
1762
ps
1380
1468
1762
ps
4–72
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009