EP2SGX130GF1508C4 Datasheet, PDF (27/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
The CRU has a built-in switchover circuit to select whether the PLL VCO
is aligned by the reference clock or the data. The optional port
rx_freqlocked monitors when the CRU is in locked-to-data mode.
In the automatic mode, the CRU PLL must be within the prescribed PPM
frequency threshold setting of the CRU reference clock for the CRU to
switch from locked-to-reference to locked-to-data mode.
The automatic switchover circuit can be overridden by using the optional
ports rx_locktorefclk and rx_locktodata. Table 2–6 shows the
possible combinations of these two signals.
Table 2–6. Receiver Lock Combinations
rx_locktodata
0
0
1
rx_locktorefclk
0
1
x
VCO (Lock to Mode)
Auto
Reference clock
Data
If the rx_locktorefclk and rx_locktodata ports are not used, the
default is auto mode.
Deserializer (Serial-to-Parallel Converter)
The deserializer converts a serial bitstream into 8, 10, 16, or 20 bits of
parallel data. The deserializer receives the LSB first. Figure 2–17 shows
the deserializer.
Altera Corporation
October 2007
2–19
Stratix II GX Device Handbook, Volume 1