EP2SGX130GF1508C4 Datasheet, PDF (289/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Figure 4–12. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions (Figure 4–13). Therefore, any distortion on the input
clock and the input clock buffer affect the output DCD.
Figure 4–13. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.