EP2SGX130GF1508C4 Datasheet, PDF (244/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Timing Model
Table 4–60. M4K Block Internal Timing Microparameters (Part 2 of 2) Note (1)
Symbol
Parameter
-3 Speed Grade
(2)
-3 Speed Grade
(3)
-4 Speed Grade
-5 Speed Grade
Unit
Min Max Min Max Min Max Min Max
t_M4KDATABH B port data hold 203
213
226
272
ps
time after clock
t_M4KRADDRBSU B port address
22
23
24
29
ps
setup time before
clock
t_M4KRADDRBH B port address
203
213
226
272
ps
hold time after
clock
t_M4KDATACO1 Clock-to-output
334 524 334 549 334 584
334 701 ps
delay when using
output registers
t_M4KDATACO2
Clock-to-output
delay without
output registers
1616 2453 1616 2574 1616 2737 1616 3286 ps
t_M4KCLKH
Minimum clock 1250
1312
1395
1675
ps
high time
t_M4KCLKL
Minimum clock 1250
1312
1395
1675
ps
low time
t_M4KCLR
Minimum clear
144
151
160
192
ps
pulse width
(1) The M512 block f_MAX obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
(2) This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
(3) This column refers to –3 speed grades for EP2SGX130 devices.
Table 4–61. M-RAM Block Internal Timing Microparameters (Part 1 of 2) Note (1)
Symbol
Parameter
t_MEGARC
Synchronous read
cycle time
t_MEGAWERESU
Write or read enable
setup time before
clock
t_MEGAWEREH Write or read enable
hold time after clock
-3 Speed
Grade (2)
Min Max
1866 2774
-3 Speed
Grade (3)
Min Max
1866 2911
-4 Speed
Grade
Min Max
1866 3096
-5 Speed
Grade _Unit
Min Max
1866 3716 ps
144
151
160
192
ps
39
40
43
52
ps
4–74
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009