EP2SGX130GF1508C4 Datasheet, PDF (104/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

PLLs and Clock Networks
Figure 2–69. External PLL Output Clock Control Blocks
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 2–69:
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
controlled during user mode operation.
(2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose
pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
For the global clock control block, the clock source selection can be
controlled either statically or dynamically. You have the option of
statically selecting the clock source by using the Quartus II software to set
specific configuration bits in the configuration file (.sof or .pof) or you can
control the selection dynamically by using internal logic to drive the
multiplexer select inputs. When selecting statically, the clock source can
be set to any of the inputs to the select multiplexer. When selecting the
clock source dynamically, you can either select between two PLL outputs
(such as the C0 or C1 outputs from one PLL), between two PLLs (such as
the C0/C1 clock output of one PLL or the C0/C1 c1ock output of the other
PLL), between two clock pins (such as CLK0 or CLK1), or between a
combination of clock pins or PLL outputs.
For the regional and PLL_OUT clock control block, the clock source
selection can only be controlled statically using configuration bits. Any of
the inputs to the clock select multiplexer can be set as the clock source.
2–96
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007