EP2SGX130GF1508C4 Datasheet, PDF (291/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Therefore, the DCD percentage for the output clock at 267 MHz is from
47.5% to 52.5%.
Table 4–99. Maximum DCD for Non-DDIO Output on Column I/O Pins
Column I/O Output ^{Maximum DCD (ps) for Non-DDIO}
Standard I/O
Output
Unit
Standard
-3 Devices -4 and -5 Devices
3.3-V LVTTL
190
220
ps
3.3-V LVCMOS
140
175
ps
2.5 V
125
155
ps
1.8 V
80
110
ps
1.5-V LVCMOS
185
215
ps
SSTL-2 Class I
105
135
ps
SSTL-2 Class II
100
130
ps
SSTL-18 Class I
90
115
ps
SSTL-18 Class II
70
100
ps
1.8-V HSTL
80
110
ps
Class I
1.8-V HSTL
80
110
ps
Class II
1.5-V HSTL
85
115
ps
Class I
1.5-V HSTL
50
80
ps
Class II
1.2-V HSTL-12
170
200
ps
LVPECL
55
80
ps