EP2SGX130GF1508C4 Datasheet, PDF (175/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 2 of 6)
Symbol /
Description
Conditions
Absolute V_{M I N}
for a REFCLK
pin (12)
Rise/fall time
Duty cycle
Peak-to-peak
differential
input voltage
Spread-
spectrum
clocking
On-chip
termination
resistors
V_{I C M} (AC
coupled) (12)
V_{I C M} (DC
coupled) (4)
Rref
Transceiver Clocks
Calibration
block clock
frequency
Calibration
block minimum
power-down
pulse width
Time taken for
one-time
calibration
fixedclk
clock
frequency
PCI Express
Receiver
Detect
Adaptive
Equalization
(AEQ)
-3 Speed Commercial
Speed Grade
Min Typ Max
-0.3
-
-
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min Typ Max Min Typ Max
-0.3
-
-
-0.3
-
-
V
-
0.2
-
-
0.2
-
-
0.2
-
UI
40
-
60
40
-
60
40
-
60
%
200
- 2000 200
-
2000 200
- 2000 mV
30
0 to
-0.5%
-
33
30
0 to 0 to
-0.5% -0.5%
-
33
30
-
33 kHz
0 to 0 to
0 to
-0.5% -0.5%
-0.5%
115 ±20%
115 ±20%
115 ±20%
Ω
1200 ±5%
1200 ±5%
1200 ±5%
mV
0.25
-
0.55 0.25
-
0.55 0.25
-
0.55
V
2000 ±1%
2000 ±1%
2000 ±1%
Ω
10
-
125
10
-
125 10
-
125 MHz
30
-
-
30
-
-
30
-
-
ns
-
-
8
-
-
8
-
-
8
ms
-
125
-
-
125
-
-
125
- MHz
2.5
-
125
2.5
-
125
-
-
- MHz
Altera Corporation
June 2009
4–5
Stratix II GX Device Handbook, Volume 1