EP2SGX130GF1508C4 Datasheet, PDF (54/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Logic Array Blocks
Figure 2–33 shows the direct link connection.
Figure 2–33. Direct Link Connection
Direct link interconnect from
left LAB, TriMatrix^TM memory
block, DSP block, or
input/output element (IOE)
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
Direct link
interconnect
to left
Local
Interconnect
Direct link
interconnect
to right
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs.
The control signals include three clocks, three clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load, and
synchronous load control signals, providing a maximum of 11 control
signals at a time. Although synchronous load and clear signals are
generally used when implementing counters, they can also be used with
other functions.
Each LAB can use three clocks and three clock enable signals. However,
there can only be up to two unique clocks per LAB, as shown in the LAB
control signal generation circuit in Figure 2–34. Each LAB’s clock and
clock enable signals are linked. For example, any ALM in a particular
LAB using the labclk1 signal also uses labclkena1. If the LAB uses
both the rising and falling edges of a clock, it also uses two LAB-wide
clock signals. De-asserting the clock enable signal turns off the
corresponding LAB-wide clock. Each LAB can use two asynchronous
clear signals and an asynchronous load/preset signal. The asynchronous
2–46
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007