EP2SGX130GF1508C4 Datasheet, PDF (102/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

PLLs and Clock Networks
Figure 2–66. EP2SGX60, EP2SGX90 and EP2SGX130 Device I/O Clock Groups
IO_CLKA[7..0]
IO_CLKB[7..0] IO_CLKC[7..0]
IO_CLKD[7..0]
8
8
8
8
8
IO_CLKP[7..0]
8
IO_CLKO[7..0]
8
IO_CLKN[7..0]
8
IO_CLKM[7..0]
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
I/O Clock Regions
8
IO_CLKE[7..0]
8
IO_CLKF[7..0]
8
IO_CLKG[7..0]
8
IO_CLKH[7..0]
8
8
8
8
IO_CLKL[7..0]
IO_CLKK[7..0]
IO_CLKJ[7..0]
IO_CLKI[7..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■ Clock source selection (dynamic selection for global clocks)
■ Clock power-down (dynamic clock enable or disable)
2–94
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007