EP2SGX130GF1508C4 Datasheet, PDF (12/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Transceivers
capable of built-in self test (BIST) generation and verification. The
ALT2GXB megafunction in the Quartus II software provides a
step-by-step menu selection to configure the transceiver.
Figure 2–1 shows the block diagram for the Stratix II GX transceiver
channel. Stratix II GX transceivers provide PCS and PMA
implementations for all supported protocols. The PCS portion of the
transceiver consists of the word aligner, lane deskew FIFO buffer, rate
matcher FIFO buffer, 8B/10B encoder and decoder, byte serializer and
deserializer, byte ordering, and phase compensation FIFO buffers.
Each Stratix II GX transceiver channel is also capable of BIST generation
and verification in addition to various loopback modes. The PMA portion
of the transceiver consists of the serializer and deserializer, the CRU, and
the high-speed differential transceiver buffers that contain pre-emphasis,
programmable on-chip termination (OCT), programmable voltage
output differential (V_OD), and equalization.
Transmitter Path
This section describes the data path through the Stratix II GX transmitter.
The Stratix II GX transmitter contains the following modules:
■ Transmitter PLLs
■ Access to one of two PLLs
■ Transmitter logic array interface
■ Transmitter phase compensation FIFO buffer
■ Byte serializer
■ 8B/10B encoder
■ Serializer (parallel-to-serial converter)
■ Transmitter differential output buffer
Transmitter PLLs
Each transceiver block has two transmitter PLLs which receive two
reference clocks to generate timing and the following clocks:
■ High-speed clock used by the serializer to transmit the high-speed
differential transmitter data
■ Low-speed clock to load the parallel transmitter data of the serializer
The serializer uses high-speed clocks to transmit data. The serializer is
also referred to as parallel in serial out (PISO). The high-speed clock is fed
to the local clock generation buffer. The local clock generation buffers
divide the high-speed clock on the transmitter to a desired frequency on
a per-channel basis. Figure 2–3 is a block diagram of the transmitter
clocks.
2–4
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007