EP2SGX130GF1508C4 Datasheet, PDF (153/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 2–42. Document Revision History (Part 3 of 6)
Date and
Document
Version
Changes Made
Moved the “Transmit State Machine” section to
after the “8B/10B Encoder” section.
Moved the “PCI Express Receiver Detect” and
“PCI Express Electric Idles (or Individual
Transmitter Tri-State)” sections to after the
“Transmit Buffer” section.
Moved the “Dynamic Reconfiguration” section
to the “Other Transceiver Features” section.
Moved the “Calibration Block”, “Receiver PLL
& CRU”, and “Deserializer (Serial-to-Parallel
Converter)” sections to the “Receiver Path”
section.
Moved the “8B/10B Decoder” and “Receiver
State Machine” sections to after the “Rate
Matcher” section.
Moved the “Byte Ordering Block” section to
after the “Byte Deserializer” section.
Updated the Clocking diagrams.
Added the “Clock Resource for PLD-
Transceiver Interface” section.
Added the “On-Chip Parallel Termination with
Calibration” section to the “On-Chip
Termination” section.
Updated:
● Table 2–2.
● Table 2–10
● Table 2–14.
● Table 2–3.
● Table 2–5.
● Table 2–8.
● Table 2–13
● Table 2–18
● Table 2–19
● Table 2–29.
Updated Figures 2–3, 2–9, 2–24, 2–25, 2–28,
2–29, 2–60, 2–62.
Change 622 Mbps to 600 Mbps throughout the
chapter.
Stratix II GX Architecture
Summary of Changes
Altera Corporation
October 2007
2–145
Stratix II GX Device Handbook, Volume 1