EP2SGX130GF1508C4 Datasheet, PDF (303/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–112. DLL Frequency Range Specifications (Part 2 of 2)
Frequency Mode
Frequency Range (MHz)
240 to 400 (–3 speed grade)
3
240 to 350 (–4 and –5 speed grade)
Resolution
(Degrees)
36
36
Table 4–113. DQS Jitter Specifications for DLL-Delayed Clock (t_DQS__JITTER)
Note (1)
Number of DQS Delay Buffer Stages
(2)
Commercial (ps)
1
80
2
110
3
130
4
160
Industrial (ps)
110
130
180
210
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
(2) Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
Table 4–114. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t_DQS__PSERR)
Number of DQS Delay Buffer Stages (1) –3 Speed Grade (ps) –4 Speed Grade (ps) –5 Speed Grade (ps)
1
25
30
35
2
50
60
70
3
75
90
105
4
100
120
140
(1) Delay stages used for request DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software. For example, phase-shift error on two delay stages under -3 conditions is 50 ps peak-to-peak or 25 ps.