EP2SGX130GF1508C4 Datasheet, PDF (165/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Configuration & Testing
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generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
For more information on the JRunner software driver, refer to the
AN 414: An Embedded Solution for PLD JTAG Configuration and the source
files on the Altera web site (www.altera.com).
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Programming Serial Configuration Devices with SRunner
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming that
can be easily customized to fit into different embedded systems. SRunner
reads a Raw Programming Data file (.rpd) and writes to serial
configuration devices. The serial configuration device programming time
using SRunner is comparable to the programming time when using the
Quartus II software.
For more information about SRunner, refer to the AN 418 SRunner: An
Embedded Solution for Serial Configuration Device Programming and the
source code on the Altera web site.
For more information on programming serial configuration devices,
refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and
EPCS128) Data Sheet in the Configuration Handbook.
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Configuring Stratix II FPGAs with the MicroBlaster Driver
The MicroBlaster software driver supports an RBF programming input
file and is ideal for embedded FPP or PS configuration. The source code
is developed for the Windows NT operating system, although it can be
customized to run on other operating systems.
For more information on the MicroBlaster software driver, refer to the
Configuring the MicroBlaster Fast Passive Parallel Software Driver White
Paper or the Configuring the MicroBlaster Passive Serial Software Driver
White Paper on the Altera web site.
PLL Reconfiguration
The phase-locked loops (PLLs) in the Stratix II GX device family support
reconfiguration of their multiply, divide, VCO-phase selection, and
bandwidth selection settings without reconfiguring the entire device. You
can use either serial data from the logic array or regular I/O pins to
program the PLL’s counter settings in a serial chain. This option provides
Altera Corporation
October 2007
3–9
Stratix II GX Device Handbook, Volume 1