EP2SGX130GF1508C4 Datasheet, PDF (116/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

PLLs and Clock Networks
Table 2–29. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL
Outputs (Part 2 of 2)
Bottom Side Global and
Regional Clock Network
Connectivity
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
Enhanced PLL 6 outputs
c0
c1
c2
c3
c4
c5
Enhanced PLL 12 outputs
c0
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
vvv
v
v
vvv
v
v
v
vv
v
v
v
vv
v
v
v
v
v
v
v
v
v
v
v
v
vv
v
v
vv
v
v
vv
v
v
vv
v
v
v
v
v
v
v
v
v
v
2–108
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007