EP2SGX130GF1508C4 Datasheet, PDF (17/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Figure 2–5. 8B/10B Encoding Process
7 6543
HG FE D
21
CB
0 ⁺ ctrl
A
8B/10B Conversion
j hg f i e dc b a
9 87 65 4 3 21 0
MSB sent last
LSB sent first
In single-width mode, the 8B/10B encoder generates a 10-bit code group
from the 8-bit data and 1-bit control identifier. In double-width mode,
there are two 8B/10B encoders that are cascaded together and generate a
20-bit (2 × 10-bit) code group from the 16-bit (2 × 8-bit) data + 2-bit
(2 × 1-bit) control identifier. Figure 2–6 shows the 20-bit encoding
process. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition
standards.
Figure 2–6. 16-Bit to 20-Bit Encoding Process
CTRL[1..0]
H' G' F' E' D' C' B' A' H G F E D C B A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Parallel Data
Cascaded 8B/10B Conversion
j' h' g' f'
i' e' d' c' b' a'
j hg
f
i
edcba
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
Upon power on or reset, the 8B/10B encoder has a negative disparity
which chooses the 10-bit code from the RD-column. However, the
running disparity can be changed via the tx_forcedisp and
tx_dispval ports.
Altera Corporation
October 2007
2–9
Stratix II GX Device Handbook, Volume 1