EP2SGX130GF1508C4 Datasheet, PDF (302/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–111. Fast PLL Specifications (Part 2 of 2)
Name
f_VCO
f_OUT
f_{OUT_EXT}
t_CONFIGPLL
f_CLBW
t_LOCK
t_{PLL_PSERR}
t_ARESET
t_{ARESET_RECONFIG}
Description
Min
Upper VCO frequency range for –3 and –4 300
speed grades
Upper VCO frequency range for –5 speed 300
grades
Lower VCO frequency range for –3 and –4 150
speed grades
Lower VCO frequency range for –5 speed 150
grades
PLL output frequency to GCLK or RCLK
4.6875
PLL output frequency to LVDS or DPA clock 150
PLL clock output frequency to regular I/O 4.6875
Time required to reconfigure scan chains for
fast PLLs
PLL closed-loop bandwidth
1.16
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
10
Minimum pulse width on the areset signal 500
when using PLL reconfiguration. Reset the
PLL after scandone goes high.
Typ
75/f_SCANCLK
5
0.03
Max
1,040
840
520
420
550
1,040
(1)
28
1
±30
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
MHz
ms
ps
ns
ns
(1) This is limited by the I/O f_MAX. See Tables 4–91 through 4–95 for the maximum.
External
Memory
Interface
Specifications
Tables 4–112 through 4–116 contain Stratix II GX device specifications for
the dedicated circuitry used for interfacing with external memory
devices.
Table 4–112. DLL Frequency Range Specifications (Part 1 of 2)
Frequency Mode
Frequency Range (MHz)
0
100 to 175
1
150 to 230
200 to 350 (–3 speed grade)
2
200 to 310 (–4 and –5 speed grade)
Resolution
(Degrees)
30
22.5
30
30