EP2SGX130GF1508C4 Datasheet, PDF (227/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 2 of 2) Notes (1), (2)
Symbol
Description
Conditions
50-Ω R_T
2.5
25-Ω R_S
1.8
50-Ω R_S
1.8
50-Ω R_T
1.8
50-Ω R_S
1.5
50-Ω R_T
1.5
50-Ω R_S
1.2
50-Ω R_T
1.2
Internal parallel termination with
calibration (50-Ω setting)
V_CCIO = 1.8 V
Internal series termination with
calibration (25-Ω setting)
V_CCIO = 1.8 V
Internal series termination without V_CCIO = 1.8 V
calibration (25-Ω setting)
Internal series termination with
calibration (50-Ω setting)
V_CCIO = 1.8 V
Internal series termination without V_CCIO = 1.8 V
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
V_CCIO = 1.8 V
Internal series termination with
calibration (50-Ω setting)
V_CCIO = 1.5 V
Internal series termination without V_CCIO = 1.5 V
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
V_CCIO = 1.5 V
Internal series termination with
calibration (50-Ω setting)
V_CCIO = 1.2 V
Internal series termination without V_CCIO = 1.2 V
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
V_CCIO = 1.2 V
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±30
± 30
%
±5
±10
%
±30
±30
%
±5
±10
%
±30
±30
%
±10
±15
%
±8
±10
%
±36
±36
%
±10
±15
%
±8
±10
%
±50
±50
%
±10
±15
%
Note for Table 4–49:
(1) The resistance tolerance for calibrated SOCT is for the moment of calibration. If the temperature or voltage changes
over time, the tolerance may also change.
(2) On-chip parallel termination with calibration is only supported for input pins.
Altera Corporation
June 2009
4–57
Stratix II GX Device Handbook, Volume 1