EP2SGX130GF1508C4 Datasheet, PDF (210/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Operating Conditions
Table 4–22. PCS Latency (Part 2 of 3) Note (1)
Functional
Mode
Configuration
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
Receiver PCS Latency
8B/10B
Decoder
Receiver Byte
State
De-
Machine serializer
8/10-bit 4-5
-
11-13
1
-
1
channel
width;
with Rate
Matcher
8/10-bit 4-5
-
-
1
-
1
channel
width;
without
Rate
BASIC _Matcher
Single
Width
16/20-bit 2-2.5
-
5.5-6.5 0.5
-
1
channel
width;
with Rate
Matcher
16/20-bit 2-2.5 -
-
0.5
-
1
channel
width;
without
Rate
Matcher
Byte
Order
1
1
1
1
Receiver
Phase
Comp
FIFO
1-2
Receiver Sum
PIPE
(2)
1 19-23
1-2
-
8-10
1-2
- 11-14
1-2
-
6-7
4–40
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009