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EP2SGX130GF1508C4 Datasheet, PDF (150/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet | |||
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Referenced Documents
Figure 2â91. Fast PLL and Channel Layout in the EP2SGX60E to EP2SGX130 Devices Note (1)
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
LVDS
4
Clock
DPA
Clock
Quadrant
Quadrant
2
Fast
PLL 8
Note to Figure 2â91:
(1) See Tables 2â39 through Tables 2â41 for the number of channels each device supports.
Referenced
Documents
This chapter references the following documents:
â DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Handbook
â DSP Blocks in Stratix II GX Devices chapter in Volume 2 of the
Stratix II GX Device Handbook
â External Memory Interfaces in Stratix II & Stratix II GX Devices chapter
in volume 2 of the Stratix II GX Device Handbook
â High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II
GX Devices chapter in volume 2 of the Stratix II GX Handbook
â PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook
â Selectable I/O Standards in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Handbook
â Stratix II GX Device Handbook, volume 2
â Stratix II GX Transceiver Architecture Overview chapter in volume 2 of
the Stratix II GX Handbook
2â142
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007
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