EP2SGX130GF1508C4 Datasheet, PDF (228/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Operating Conditions
Table 4–50. Series and Differential On-Chip Termination Specification for Left I/O Banks Note (1)
Symbol
Description
Conditions
25-Ω R_S
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
50-Ω R_S
Internal series termination without
3.3/2.5/1.8 calibration (50-Ω setting)
50-Ω R_S 1.5 Internal series termination without
calibration (50-Ω setting)
R_D
Internal differential termination for
LVDS (100-Ω setting)
V_CCIO = 3.3/2.5V
V_CCIO = 3.3/2.5/1.8V
V_CCIO = 1.5V
V_CCIO = 2.5 V
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±30
±30
%
±30
±30
%
±36
±36
%
±20
±25
%
Note to Table 4–50:
(1) On-chip parallel termination with calibration is only supported for input pins.
Pin Capacitance
Table 4–51 shows the Stratix II GX device family pin capacitance.
Table 4–51. Stratix II GX Device Capacitance Note (1)
Symbol
Parameter
Typical Unit
C_IOTB
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
5.0
pF
C_IOL
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed
6.1
pF
differential receiver and transmitter pins.
C_CLKTB
Input capacitance on top/bottom clock input pins: CLK[4..7] and
CLK[12..15].
6.0
pF
C_CLKL
Input capacitance on left clock inputs: CLK0 and CLK2.
6.1
pF
C_CLKL+
Input capacitance on left clock inputs: CLK1 and CLK3.
3.3
pF
C_OUTFB
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 11 and 12.
6.7
pF
Note to Table 4–51:
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
4–58
Stratix II GX Device Handbook, Volume 1
Altera Corporation
June 2009