EP2SGX130GF1508C4 Datasheet, PDF (115/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Stratix II GX Architecture
Table 2–28. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 2 of 2)
Top Side Global and
Regional Clock Network
Connectivity
c2
c3
c4
c5
Enhanced PLL 11 outputs
c0
c1
c2
c3
c4
c5
v
vv
v
v
v
vv
v
v
v
v
v
v
v
v
v
v
v
v
vv
v
v
vv
v
v
vv
v
v
vv
v
v
v
v
v
v
v
v
v
v
Table 2–29. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL
Outputs (Part 1 of 2)
Bottom Side Global and
Regional Clock Network
Connectivity
Clock pins
CLK4p
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
vvv
v
v
vvv
v
v
v
vv
v
v
v
vv
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
October 2007
2–107
Stratix II GX Device Handbook, Volume 1