EP2SGX130GF1508C4 Datasheet, PDF (28/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Transceivers
Figure 2–17. Deserializer Note (1)
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
10
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
High-speed
serial clock
Low-speed
parallel clock
Note to Figure 2–17:
(1) This is a 10-bit deserializer. The deserializer can also convert 8, 16, or 20 bits of data.
Word Aligner
The deserializer block creates 8-, 10-, 16-, or 20-bit parallel data. The
deserializer ignores protocol symbol boundaries when converting this
data. Therefore, the boundaries of the transferred words are arbitrary. The
word aligner aligns the incoming data based on specific byte or word
boundaries. The word alignment module is clocked by the local receiver
recovered clock during normal operation. All the data and programmed
patterns are defined as big-endian (most significant word followed by
least significant word). Most-significant-bit-first protocols such as
SONET/SDH should reverse the bit order of word align patterns
programmed.
2–20
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007