EP2SGX130GF1508C4 Datasheet, PDF (179/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 6 of 6)
Symbol /
Description
Conditions
Bandwidth at
6.375 Gbps
BW = Low
BW = Med
BW = High
Bandwidth at
3.125 Gbps
BW = Low
BW = Med
BW = High
Bandwidth at
2.5 Gbps
BW = Low
BW = Med
BW = High
TX PLL lock
time from
gxb_
powerdown
deassertion
(9), (10)
PLD-Transceiver Interface
Interface
speed
Digital Reset
Pulse Width
-3 Speed Commercial
Speed Grade
Min Typ Max
-
2
-
-
3
-
-
7
-
-
3
-
-
5
-
-
9
-
-
1
-
-
2
-
-
4
-
-
-
100
-4 Speed Commercial
and Industrial Speed
Grade
-5 Speed Commercial
Speed Grade
Unit
Min Typ Max Min Typ Max
-
-
-
-
-
-
MHz
-
-
-
-
-
-
MHz
-
-
-
-
-
-
MHz
-
3
-
-
3
-
MHz
-
5
-
-
5
-
MHz
-
9
-
-
9
-
MHz
-
1
-
-
1
-
MHz
-
2
--
-
2
-
MHz
-
4
-
-
4
-
MHz
-
-
100
-
-
100 us
25
-
250
25
-
250 25
-
200 MHz
Minimum is 2 parallel clock cycles
Notes to Table 4–6:
(1) The device cannot tolerate prolonged operation at this absolute maximum. Refer to Figure 4–5 for more information.
(2) The rate matcher supports only up to +/-300 ppm.
(3) This parameter is measured by embedding the run length data in a PRBS sequence.
(4) This feature is only available in PCI-Express (PIPE) mode.
(5) Time taken to rx_pll_locked goes high from rx_analogreset deassertion. Refer to Figure 4–1.
(6) This is how long GXB needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is
asserted in manual mode. Refer to Figure 4–1.
(7) Time taken to recover valid data from GXB after rx_locktodata signal is asserted in manual mode. Measurement
results are based on PRBS31, for native data rates only. Refer to Figure 4–1.
(8) Time taken to recover valid data from GXB after rx_freqlocked signal goes high in automatic mode. Measurement
results are based on PRBS31, for native data rates only. Refer to Figure 4–1.
(9) Please refer to the Protocol Characterization documents for lock times specific to the protocols.
(10) Time taken to lock TX PLL from gxb_powerdown deassertion.
(11) The 1.2 V RX V_ICM setting is intended for DC-coupled LVDS links.
(12) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Make sure that input
specifications are not violated during this period.
Altera Corporation
June 2009
4–9
Stratix II GX Device Handbook, Volume 1