EP2SGX130GF1508C4 Datasheet, PDF (209/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

DC and Switching Characteristics
Table 4–22. PCS Latency (Part 1 of 3) Note (1)
Receiver PCS Latency
Functional
Mode
Configuration
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
8B/10B
Decoder
Receiver Byte
State
De-
Machine serializer
XAUI
2-2.5 2-2.5 5.5-6.5 0.5
1
1
×1, ×4, ×8 4-5
-
11-13
1
-
1
8-bit
channel
width
PIPE
×1, ×4, ×8 2-2.5 - 5.5-6.5 0.5
-
1
16-bit
channel
width
GIGE
4-5
-
11-13
1
-
1
OC-12
6-7
-
-
1
-
1
SONET/
SDH
OC-48
3-3.5
-
-
0.5
-
1
OC-96 2-2.5 -
-
0.5
-
1
(OIF)
CEI
PHY
2.5
-
-
0.5
-
1
CPRI 614 Mbps, 4-5
-
-
1
-
1
(4)
1.228 Gbps
2.456 Gbps 4-5
-
-
1
-
1
Serial 1.25 Gbps, 2-2.5 -
-
0.5
-
1
RapidIO 2.5 Gbps,
3.125 Gbps
SDI
HD
5
-
-
1
-
1
10-bit
channel
width
HD, 3G 2.5
-
-
0.5
-
1
20-bit
channel
width
Byte
Order
1
1
1
1
1
1-2
1
1
1
1
1
1
1
Receiver
Phase
Comp
FIFO
1-2
2-3
Receiver Sum
PIPE
(2)
- 14-17
1 21-25
2-3
1 13-16
1-2
- 19-23
1-2
- 10-12
1-2
-
7-9
1-2
-
6-7
1-2
-
6-7
1
-
8-9
1-2
-
8-10
1-2
-
6-7
1-2
-
9-10
1-2
-
6-7
Altera Corporation
June 2009
4–39
Stratix II GX Device Handbook, Volume 1