EP2SGX130GF1508C4 Datasheet, PDF (11/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Altera Corporation
October 2007
Stratix II GX Architecture
Figure 2–2. Elements of the Transceiver Block
Stratix II GX
Logic Array
Transceiver Block
Channel 1
Channel 0
Supporting Blocks
(PLLs, State Machines,
Programming)
Channel 2
Channel 3
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
Each Stratix II GX transceiver channel consists of a transmitter and
receiver. The transceivers are grouped in four and share PLL resources.
Each transmitter has access to one of two PLLs. The transmitter contains
the following:
■ Transmitter phase compensation first-in first-out (FIFO) buffer
■ Byte serializer (optional)
■ 8B/10B encoder (optional)
■ Serializer (parallel-to-serial converter)
■ Transmitter differential output buffer
The receiver contains the following:
■ Receiver differential input buffer
■ Receiver lock detector and run length checker
■ Clock recovery unit (CRU)
■ Deserializer
■ Pattern detector
■ Word aligner
■ Lane deskew
■ Rate matcher (optional)
■ 8B/10B decoder (optional)
■ Byte deserializer (optional)
■ Byte ordering
■ Receiver phase compensation FIFO buffer
Designers can preset Stratix II GX transceiver functions using the
Quartus^® II software. In addition, pre-emphasis, equalization, and
differential output voltage (V_OD) are dynamically programmable. Each
Stratix II GX transceiver channel supports various loopback modes and is
2–3
Stratix II GX Device Handbook, Volume 1