EP2SGX130GF1508C4 Datasheet, PDF (294/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2) Note (1)
Maximum DCD (ps) for
Input IO Standard (No PLL in the Clock Path)
DDIO Column Output I/O
TTL/CMOS
SSTL-2 SSTL/HSTL HSTL12
Unit
Standard
3.3/2.5V 1.8/1.5V
2.5V
1.8/1.5V
1.2V
SSTL-18 Class II
140
260
70
70
70
ps
1.8-V HSTL Class I
150
270
60
60
60
ps
1.8-V HSTL Class II
150
270
60
60
60
ps
1.5-V HSTL Class I
150
270
55
55
55
ps
1.5-V HSTL Class II
125
240
85
85
85
ps
1.2-V HSTL
240
360
155
155
155
ps
LVPECL
180
180
180
180
180
ps
(1) Table 4–102 assumes the input clock has zero DCD.
Table 4–103. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and
-5 Devices Note (1)
Maximum DCD (ps) for
Input IO Standard (No PLL in the Clock Path)
DDIO Column Output I/O
TTL/CMOS
SSTL-2
SSTL/HSTL
Unit
Standard
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3-V LVTTL
3.3-V LVCMOS
440
495
170
160
ps
390
450
120
110
ps
2.5 V
1.8 V
375
430
105
95
ps
325
385
90
100
ps
1.5-V LVCMOS
430
490
160
155
ps
SSTL-2 Class I
SSTL-2 Class II
355
410
85
350
405
80
75
ps
70
ps
SSTL-18 Class I
SSTL-18 Class II
335
390
65
320
375
70
65
ps
80
ps
1.8-V HSTL Class I
330
1.8-V HSTL Class II
330
385
60
385
60
70
ps
70
ps
1.5-V HSTL Class I
330
390
60
70
ps
1.5-V HSTL Class II
330
LVPECL
180
360
90
180
180
100
ps
180
ps
(1) Table 4–103 assumes the input clock has zero DCD.