EP2SGX130GF1508C4 Datasheet, PDF (118/316 Pages) Altera Corporation – Section I. Stratix II GX Device Data Sheet

I/O Structure
Figure 2–75. Stratix II GX Device Fast PLL
Global or
regional clock (1)
Clock
Switchover
Circuitry (4)
Phase
Frequency
Detector
VCO Phase Selection
Selectable at each PLL
Output Port
Post-Scale
Counters
÷c0
diffioclk0 (2)
load_en0 (3)
Clock
Input
4
÷n
PFD
Charge
Pump
Loop
Filter
VCO
8
÷k
Global or
regional clock (1)
÷m
Shaded Portions of the
PLL are Reconfigurable
÷c1
÷c2
4
÷c3
load_en1 (3)
diffioclk1 (2)
4
Global clocks
8
Regional clocks
8
to DPA block
Notes to Figure 2–75:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES)
circuitry. Stratix II GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O
support mode.
(3) This signal is a differential I/O SERDES control signal.
(4) Stratix II GX fast PLLs only support manual clock switchover.
f
Refer to the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II GX Device Handbook for more information on enhanced
and fast PLLs. Refer to “High-Speed Differential I/O with DPA Support”
on page 2–136 for more information on high-speed differential I/O
support.
I/O Structure
The Stratix II GX IOEs provide many features, including:
■ Dedicated differential and single-ended I/O buffers
■ 3.3-V, 64-bit, 66-MHz PCI compliance
■ 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■ Joint Test Action Group (JTAG) boundary-scan test (BST) support
■ On-chip driver series termination
■ On-chip termination for differential standards
■ Programmable pull-up during configuration
■ Output drive strength control
■ Tri-state buffers
■ Bus-hold circuitry
■ Programmable pull-up resistors
■ Programmable input and output delays
2–110
Stratix II GX Device Handbook, Volume 1
Altera Corporation
October 2007