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DS077 Datasheet, PDF (89/108 Pages) Xilinx, Inc – Product Availability
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Spartan-IIE FPGA Family: Pinout Tables
Additional FG456 Package Pins (Continued)
VCCO Bank 1 Pins
F15
F16
G13
G14
-
-
-
-
-
VCCO Bank 2 Pins
G17
H17
J16
K16
-
-
-
-
-
VCCO Bank 3 Pins
N16
P16
R17
T17
-
-
-
-
-
VCCO Bank 4 Pins
T13
T14
U15
U16
-
-
-
-
-
VCCO Bank 5 Pins
T9
T10
U7
U8
-
-
-
-
-
VCCO Bank 6 Pins
N7
P7
R6
T6
-
-
-
-
-
VCCO Bank 7 Pins
G6
H6
J7
K7
-
-
-
-
-
GND Pins
A1
A2(2)
A22
B1(2)
B2
B21
C3
C20
G11
G12
J9
J10
J11
J12
J13
J14
K9
K10
K11
K12
K13
K14
L7
L9
L10
L11
L12
L13
L14
L16
M7
M9
M10
M11
M12
M13
M14
M16
N9
N10
N11
N12
N13
N14
P9
P10
P11
P12
P13
P14
T11
T12
Y20
Y3
Y4(2)
AA2
AA4(2)
AA21
AA22(2)
AB1
AB22
-
-
Not Connected Pins
A2(2)
B1(2)
D4(1)
D19(1)
W4(1)
W19(1)
Y4(2)
AA4(2)
AA22(2)
Notes:
1. VCCINT connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E,
and XC2S300E.
2. GND connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E, and
XC2S300E
FG676 Pinouts (XC2S400E, XC2S600E)
Pad Name
Function
Bank Pin
LVDS Async.
Output Option
TMS
-
B1
-
I/O
7
D3
-
I/O, L204P
7
C2
-
I/O, L204N
7
C1
-
I/O, L203P
7
D2
XC2S600E
I/O, L203N
7
D1
XC2S600E
I/O, L202P_YY
7
E2
All
I/O, L202N_YY
7
E1
All
VREF
Option
-
-
-
-
-
-
-
-
DS077-4 (2.3) June 18, 2008
Product Specification
www.xilinx.com
Device-Specific Pinouts
XC2S400E
XC2S600E
TMS
TMS
I/O
I/O
-
I/O, L204P
-
I/O, L204N
-
I/O, L203P_Y
I/O
I/O, L203N_Y
I/O, L202P_YY
I/O, L202P_YY
I/O, L202N_YY
I/O, L202N_YY
89
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