DS077 Datasheet, PDF(41/108 Page) Xilinx, Inc

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DS077 Datasheet, PDF (41/108 Pages) Xilinx, Inc – Product Availability

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Spartan-IIE FPGA Family: DC and Switching Characteristics

Calculation of TIOOP as a Function of

Capacitance

TIOOP is the propagation delay from the O Input of the IOB

to the pad. The values for TIOOP are based on the standard

capacitive load (CSL) for each I/O standard as listed in the

table Constants for Calculating TIOOP, below.

For other capacitive loads, use the formulas below to calcu-

late an adjusted propagation delay, TIOOP1.

TIOOP1 = TIOOP + Adj + (CLOAD â CSL) * FL

Where:

Adj is selected from IOB Output Delay Adjustments

for Different Standards(1), page 40, according

to the I/O standard used

CLOAD is the capacitive load for the design

is the capacitance scaling factor

Delay Measurement Methodology

Standard

LVTTL

VL(1)

VH (1)

Meas. VREF

Point Typ(2)

1.4

LVCMOS2

2.5

1.125 -

PCI33_3

Per PCI Spec

PCI66_3

Per PCI Spec

GTL

VREF â 0.2 VREF + 0.2

GTL+

VREF â 0.2 VREF + 0.2

HSTL Class I VREF â 0.5 VREF + 0.5

HSTL Class III VREF â 0.5 VREF + 0.5

HSTL Class IV VREF â 0.5 VREF + 0.5

SSTL3 I and II VREF â 1.0 VREF + 1.0

SSTL2 I and II VREF â 0.75 VREF + 0.75

CTT

VREF â 0.2 VREF + 0.2

AGP

VREF â

VREF +

(0.2xVCCO) (0.2xVCCO)

LVDS

1.2 â 0.125 1.2 + 0.125

VREF

1.2

0.80

1.0

0.75

0.90

1.5

1.25

1.5

Per AGP

Spec

LVPECL

1.6 â 0.3 1.6 + 0.3 1.6

Notes:

1. Input waveform switches between VL and VH.

2. Measurements are made at VREF Typ, Maximum, and

Minimum. Worst-case values are reported.

3. I/O parameter measurements are made with the capacitance

values shown in the following table, Constants for Calculating

TIOOP. Refer to Application Note XAPP179 for appropriate

terminations.

4. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

Constants for Calculating TIOOP

Standard

CSL(1)

(pF)

(ns/pF)

LVTTL Fast Slew Rate, 2 mA drive

35 0.41

LVTTL Fast Slew Rate, 4 mA drive

35 0.20

LVTTL Fast Slew Rate, 6 mA drive

35 0.13

LVTTL Fast Slew Rate, 8 mA drive

35 0.079

LVTTL Fast Slew Rate, 12 mA drive

35 0.044

LVTTL Fast Slew Rate, 16 mA drive

35 0.043

LVTTL Fast Slew Rate, 24 mA drive

35 0.033

LVTTL Slow Slew Rate, 2 mA drive

35 0.41

LVTTL Slow Slew Rate, 4 mA drive

35 0.20

LVTTL Slow Slew Rate, 6 mA drive

35 0.100

LVTTL Slow Slew Rate, 8 mA drive

35 0.086

LVTTL Slow Slew Rate, 12 mA drive

35 0.058

LVTTL Slow Slew Rate, 16 mA drive

35 0.050

LVTTL Slow Slew Rate, 24 mA drive

35 0.048

LVCMOS2

35 0.041

LVCMOS18

35 0.050

PCI 33 MHz 3.3V

10 0.050

PCI 66 MHz 3.3V

10 0.033

GTL

0 0.014

GTL+

0 0.017

HSTL Class I

20 0.022

HSTL Class III

20 0.016

HSTL Class IV

20 0.014

SSTL2 Class I

30 0.028

SSTL2 Class II

30 0.016

SSTL3 Class I

30 0.029

SSTL3 Class II

30 0.016

CTT

20 0.035

AGP

10 0.037

Notes:

1. I/O parameter measurements are made with the capacitance

values shown above. Refer to Application Note XAPP179 for

appropriate terminations.

2. I/O standard measurements are reflected in the IBIS model

information except where the IBIS format precludes it.

DS077-3 (v2.3) June 18, 2008

www.xilinx.com

Product Specification

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