DS077 Datasheet, PDF (40/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: DC and Switching Characteristics
R
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Output Delay Adjustments (Adj)
T_{OLVTTL_S2}
Standard-specific adjustments for LVTTL, Slow, 2 mA
14.7
14.7
ns
T_{OLVTTL_S4}
T_{OLVTTL_S6}
output delays terminating at pads
(based on standard capacitive
load, C_SL)
4 mA
7.5
6 mA
4.8
7.5
ns
4.8
ns
T_{OLVTTL_S8}
8 mA
3.0
3.0
ns
T_{OLVTTL_S12}
12 mA
1.9
1.9
ns
T_{OLVTTL_S16}
16 mA
1.7
1.7
ns
T_{OLVTTL_S24}
24 mA
1.3
1.3
ns
T_{OLVTTL_F2}
LVTTL, Fast, 2 mA
13.1
13.1
ns
T_{OLVTTL_F4}
4 mA
5.3
5.3
ns
T_{OLVTTL_F6}
6 mA
3.1
3.1
ns
T_{OLVTTL_F8}
8 mA
1.0
1.0
ns
T_{OLVTTL_F12}
12 mA
0
0
ns
T_{OLVTTL_F16}
16 mA
–0.05
–0.05
ns
T_{OLVTTL_F24}
24 mA
–0.20
–0.20
ns
T_OLVCMOS2
LVCMOS2
0.09
0.09
ns
T_OLVCMOS18
LVCMOS18
0.7
0.7
ns
T_OLVDS
LVDS
–1.2
–1.2
ns
T_OLVPECL
LVPECL
–0.41
–0.41
ns
T_{OPCI33_3}
PCI, 33 MHz, 3.3V
2.3
2.3
ns
T_{OPCI66_3}
PCI, 66 MHz, 3.3V
–0.41
–0.41
ns
T_OGTL
GTL
0.49
0.49
ns
T_OGTLP
GTL+
0.8
0.8
ns
T_{OHSTL_I}
HSTL I
–0.51
–0.51
ns
T_{OHSTL_III}
HSTL III
–0.91
–0.91
ns
T_{OHSTL_IV}
HSTL IV
–1.01
–1.01
ns
T_{OSSTL2_I}
SSTL2 I
–0.51
–0.51
ns
T_{OSSLT2_II}
SSTL2 II
–0.91
–0.91
ns
T_{OSSTL3_I}
SSTL3 I
–0.51
–0.51
ns
T_{OSSTL3_II}
SSTL3 II
–1.01
–1.01
ns
T_OCTT
CTT
–0.61
–0.61
ns
T_OAGP
AGP
–0.91
–0.91
ns
Notes:
1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 41.
40
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DS077-3 (v2.3) June 18, 2008
Product Specification