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DS077 Datasheet, PDF (66/108 Pages) Xilinx, Inc – Product Availability
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Spartan-IIE FPGA Family: Pinout Tables
R
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E,
XC2S400E)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
TMS
-
B1
-
-
I/O
7 D3
-
-
I/O, L83P
7 C2 XC2S100E,
-
150E
I/O, L83N
7 C1 XC2S100E, XC2S200E,
150E 300E, 400E
I/O, L82P_YY 7 D2
All
-
I/O, L82N_YY 7 D1
All
-
I/O, VREF
7 E3 XC2S50E,
All
Bank 7, L81P
150E, 200E,
300E, 400E
I/O, L81N
7 E4 XC2S50E,
-
150E, 200E,
300E, 400E
I/O, L80P
7 E2 XC2S200E,
-
400E
I/O, L80N
7 E1 XC2S200E,
-
400E
I/O, L79P
7
F4 XC2S50E, XC2S100E,
300E, 400E 150E, 200E,
300E, 400E
I/O, L79N
7
F3 XC2S50E,
-
300E, 400E
I/O, L78P_YY 7
F2
All
-
I/O, L78N_YY 7
F1
All
-
I/O, L77P
7
F5 XC2S100E,
-
150E
I/O, L77N
7 G5 XC2S100E,
-
150E
I/O, L76P_YY 7 G3
All
-
I/O, L76N_YY 7 G4
All
-
I/O, VREF
7 G2 XC2S50E,
All
Bank 7, L75P
300E, 400E
I/O, L75N
7 G1 XC2S50E,
-
300E, 400E
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L74P
7 H4 XC2S100E,
-
150E, 200E
I/O, L74N
7 H3 XC2S100E, XC2S400E
150E, 200E
I/O, L73P_YY 7 H2
All
-
I/O (IRDY),
7 H1
All
-
L73N_YY
I/O (TRDY)
6
J4
-
-
I/O, L72P
6
J2 XC2S100E, XC2S400E
150E, 200E,
400E
I/O, L72N
6
J3 XC2S100E,
-
150E, 200E,
400E
I/O, L71P
6
J1 XC2S50E,
-
300E, 400E
I/O, VREF
6 K1 XC2S50E,
All
Bank 6, L71N
300E, 400E
I/O, L70P_YY 6 K2
All
-
I/O, L70N_YY 6 K3
All
-
I/O, L69P
6 L1 XC2S100E,
-
150E, 400E
I/O, L69N
6 L2 XC2S100E,
-
150E, 400E
I/O, L68P_YY 6 K4
All
-
I/O, L68N_YY 6 K5
All
-
I/O, L67P
6 L3 XC2S50E,
-
300E, 400E
I/O, L67N
6 M2 XC2S50E, XC2S100E,
300E, 400E 150E, 200E,
300E, 400E
I/O, L66P
6 M1 XC2S150E,
-
200E, 400E
I/O, L66N
6 N1 XC2S150E,
-
200E, 400E
66
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DS077-4 (2.3) June 18, 2008
Product Specification
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