DS077 Datasheet, PDF (10/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: Functional Description
R
T
CLK
TCE
SR
O
OCE
SR
D
Q
TFF
CK
EC
SR
D
Q
OFF
CK
EC
IQ
SR
I
D
Q
IFF
CK
ICE
EC
Notes:
1. For some I/O standards.
V_CC
OE
Programmable
Bias and
ESD Network
V_CCO
Package
Pin
I/O
Package Pin
Programmable
Output Buffer
Programmable
Delay
V_CC(1)
Programmable
Input Buffer
Internal
Reference
I/O, V_REF
Package Pin
To Next I/O
To Other
External V_REF Inputs
of Bank
DS077-2_01_051501
Figure 4: Spartan-IIE Input/Output Block (IOB)
Table 3: Standards Supported by I/O (Typical Values)
I/O Standard
LVTTL (2-24 mA)
Input
Output Board
Reference Input Source Termination
Voltage Voltage Voltage Voltage
(V_REF) (V_CCO) (V_CCO)
(V_TT)
N/A
3.3
3.3
N/A
LVCMOS2
N/A
2.5
2.5
N/A
LVCMOS18
N/A
1.8
1.8
N/A
PCI (3V,
N/A
3.3
3.3
N/A
33 MHz/66 MHz)
GTL
0.8
N/A N/A
1.2
GTL+
1.0
N/A N/A
1.5
HSTL Class I
0.75
N/A
1.5
0.75
HSTL Class III
0.9
N/A
1.5
1.5
HSTL Class IV
0.9
N/A
1.5
1.5
SSTL3 Class I
1.5
N/A
3.3
1.5
and II
SSTL2 Class I
1.25
N/A
2.5
1.25
and II
CTT
1.5
N/A
3.3
1.5
AGP
1.32
N/A
3.3
N/A
LVDS, Bus LVDS
N/A
N/A
2.5
N/A
LVPECL
N/A
N/A
3.3
N/A
Input/Output Block
The Spartan-IIE FPGA IOB, as seen in Figure 4, features
inputs and outputs that support a wide variety of I/O signal-
ing standards. These high-speed inputs and outputs are
capable of supporting various state of the art memory and
bus interfaces. The default standard is LVTTL. Table 3 lists
several of the standards which are supported along with the
required reference (V_REF), output (V_CCO) and board termi-
nation (V_TT) voltages needed to meet the standard. For
more details on the I/O standards and termination applica-
tion examples, see XAPP179, "Using SelectIO Interfaces in
Spartan-II and Spartan-IIE FPGAs."
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
In addition to the CLK and CE control signals, the three reg-
isters share a Set/Reset (SR). For each register, this signal
can be independently configured as a synchronous Set, a
synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
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DS077-2 (v2.3) June 18, 2008
Product Specification