DS077 Datasheet, PDF(58/108 Page) Xilinx, Inc

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DS077 Datasheet, PDF (58/108 Pages) Xilinx, Inc – Product Availability

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Spartan-IIE FPGA Family: Pinout Tables

Pinout Tables

The following device-specific pinout tables include all pack-

ages available for each Spartan-IIE device. They follow the

pad locations around the die. In the TQ144 package, all

VCCO pins must be connected to the same voltage.

TQ144 Pinouts (XC2S50E and XC2S100E)

Pad Name

Function Bank Pin

LVDS

Async.

Output

Option

VREF

Option

GND

TMS

I/O

I/O, VREF

All

Bank 7

I/O

I/O, L27P

P7 XC2S50E XC2S100E

I/O, L27N

P8 XC2S50E

GND

I/O, L26P_YY

7 P10

All

I/O, L26N_YY

7 P11

All

I/O, VREF

7 P12 XC2S50E

All

Bank 7, L25P

I/O, L25N

7 P13 XC2S50E

I/O

7 P14

I/O (IRDY)

7 P15

GND

- P16

VCCO

- P17

I/O (TRDY)

6 P18

VCCINT

- P19

I/O

6 P20

I/O, L24P

6 P21 XC2S50E

I/O, VREF

6 P22 XC2S50E

All

Bank 6, L24N

I/O, L23P_YY

6 P23

All

I/O, L23N_YY

6 P24

All

GND

- P25

I/O, L22P

6 P26 XC2S50E

TQ144 Pinouts (XC2S50E and XC2S100E)

(Continued)

Pad Name

Function Bank Pin

LVDS

Async.

Output

Option

VREF

Option

I/O, L22N

6 P27 XC2S50E XC2S100E

I/O

6 P28

I/O, VREF

6 P29

All

Bank 6

I/O

6 P30

I/O, L21P_YY

6 P31

All

I/O, L21N_YY

6 P32

All

- P33

GND

- P34

- P35

VCCO

- P36

- P37

I/O, L20N_YY

5 P38

I/O, L20P_YY

5 P39

I/O

5 P40

I/O, VREF

Bank 5

5 P41

I/O

5 P42

I/O, L19N_YY

5 P43

I/O, L19P_YY

5 P44

GND

- P45

VCCINT

- P46

I/O, L18N_YY

5 P47

I/O, L18P_YY

5 P48

I/O, VREF

Bank 5

5 P49

I/O (DLL), L17N 5 P50

VCCINT

- P51

GCK1, I

5 P52

VCCO

5 P53

GND

- P54

All

XC2S100E

All

GCK0, I

4 P55

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DS077-4 (2.3) June 18, 2008

Product Specification

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