DS077 Datasheet, PDF (11/108 Pages) Xilinx, Inc – Product Availability

R
Spartan-IIE FPGA Family: Functional Description
Optional pull-up and pull-down resistors and an optional
weak-keeper circuit are attached to each user I/O pad. Prior
to configuration all outputs not involved in configuration are
forced into their high-impedance state. The pull-down resis-
tors and the weak-keeper circuits are inactive, but inputs
may optionally be pulled up. The activation of pull-up resis-
tors prior to configuration is controlled on a global basis by
the configuration mode pins. If the pull-up resistors are not
activated, all the pins will float. Consequently, external
pull-up or pull-down resistors must be provided on pins
required to be at a well-defined logic level prior to configura-
tion.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to V_CCO for
LVTTL, PCI, HSTL, SSTL, CTT, and AGP standards.
All Spartan-IIE FPGA IOBs support IEEE 1149.1-compati-
ble boundary scan testing.
Input Path
A buffer in the IOB input path routes the input signal directly
to internal logic and through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V_REF. The need to supply V_REF imposes
constraints on which standards can used in close proximity
to each other. See I/O Banking.
There are optional pull-up and pull-down resistors at each
input for use after configuration.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients. The
default output driver is LVTTL with 12 mA drive strength and
slow slew rate.
In most signaling standards, the output high voltage
depends on an externally supplied V_CCO voltage. The need
to supply V_CCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
ing.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way helps eliminate bus chatter.
Because the weak-keeper circuit uses the IOB input buffer
to monitor the input level, an appropriate V_REF voltage must
be provided if the signaling standard requires one. The pro-
vision of this voltage must comply with the I/O banking
rules.
I/O Banking
Some of the I/O standards described above require V_CCO
and/or V_REF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks (see Figure 5). The pinout tables
show the bank affiliation of each I/O (see Pinout Tables,
page 53). Each bank has multiple V_CCO pins which must be
connected to the same voltage. Voltage requirements are
determined by the output standards in use.
Bank 0
Bank 1
GCLK3 GCLK2
Spartan-IIE
Device
GCLK1 GCLK0
Bank 5
Bank 4
DS077-2_02_051501
Figure 5: Spartan-IIE I/O Banks
In the TQ144 and PQ208 packages, the eight banks have
V_CCO connected together. Thus, only one V_CCO level is
allowed in these packages, although different V_REF values
are allowed in each of the eight banks.
Within a bank, standards may be mixed only if they use the
same V_CCO. Compatible standards are shown in Table 4.
GTL and GTL+ appear under all voltages because their
open-drain outputs do not depend on V_CCO. Note that V_CCO
DS077-2 (v2.3) June 18, 2008
www.xilinx.com
11
Product Specification