DS077 Datasheet, PDF (3/108 Pages) Xilinx, Inc – Product Availability

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DS077-1 (v2.3) June 18, 2008
Spartan-IIE FPGA Family:
Introduction and Ordering
Information
0 Product Specification
Introduction
The Spartan^®-IIE Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
seven-member family offers densities ranging from 50,000
to 600,000 system gates, as shown in Table 1. System per-
formance is supported beyond 200 MHz.
Features include block RAM (to 288K bits), distributed RAM
(to 221,184 bits), 19 selectable I/O standards, and four
DLLs (Delay-Locked Loops). Fast, predictable interconnect
means that successive design iterations continue to meet
timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 15,552 logic cells with up to
600,000 system gates
- Streamlined features based on Virtex^®-E FPGA
architecture
- Unlimited in-system reprogrammability
- Very low cost
- Cost-effective 0.15 micron technology
• System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
- Low-power segmented routing architecture
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
· Eliminate clock distribution delay
· Multiply, divide, or phase shift
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards
· LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL
· LVDS and LVPECL differential I/O
- Up to 205 differential I/O pairs that can be input,
output, or bidirectional
- Hot swap I/O (CompactPCI friendly)
• Core logic powered at 1.8V and I/Os powered at 1.5V,
2.5V, or 3.3V
• Fully supported by powerful Xilinx^® ISE^® development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
- Extensive IP library including DSP functions and
soft processors
Table 1: Spartan-IIE FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O⁽¹⁾
Maximum
Differential
I/O Pairs
Distributed Block RAM
RAM Bits
Bits
XC2S50E 1,728
23,000 - 50,000
16 x 24 384
182
83
24,576
32K
XC2S100E 2,700
37,000 - 100,000
20 x 30 600
202
86
38,400
40K
XC2S150E 3,888
52,000 - 150,000
24 x 36 864
265
114
55,296
48K
XC2S200E 5,292
71,000 - 200,000
28 x 42 1,176
289
120
75,264
56K
XC2S300E 6,912
93,000 - 300,000
32 x 48 1,536
329
120
98,304
64K
XC2S400E 10,800
145,000 - 400,000
40 x 60 2,400
410
172
153,600
160K
XC2S600E 15,552
210,000 - 600,000
48 x 72 3,456
514
205
221,184
288K
Notes:
1. User I/O counts include the four global clock/user input pins. See details in Table 2, page 5
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DS077-1 (v2.3) June 18, 2008
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Product Specification