English
Language : 

DS077 Datasheet, PDF (70/108 Pages) Xilinx, Inc – Product Availability
◁
Spartan-IIE FPGA Family: Pinout Tables
R
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L20P
2 D14 XC2S100E, XC2S200E,
200E, 300E 300E, 400E
I/O (DIN, D0), 2 B16
All
-
L19N_YY
I/O (DOUT,
2 C15
All
-
BUSY),
L19P_YY
CCLK
2 A15
-
-
TDO
2 B14
-
-
TDI
- C13
-
-
I/O (CS),
1 A14
All
-
L18P_YY
I/O (WRITE), 1 A13
All
-
L18N_YY
I/O, L17P
1 B13 XC2S50E, XC2S200E,
100E, 200E, 300E, 400E
300E, 400E
I/O, L17N
1 C12 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L16P_YY 1 B12
All
-
I/O, L16N_YY 1 A12
All
-
I/O, VREF
1 D12
All
All
Bank 1,
L15P_YY
I/O, L15N_YY 1 E11
All
-
I/O, L14P
1 D11 XC2S50E,
-
100E, 150E,
300E
I/O, L14N
1 C11 XC2S50E,
-
100E, 150E,
300E
I/O, L13P
1 B11 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E, 400E 300E, 400E
I/O, L13N
1 A11 XC2S50E,
-
100E, 200E,
300E, 400E
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L12P
1 E10 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L12N
1 D10 XC2S50E,
-
100E, 200E,
300E, 400E
I/O
1 C10
-
-
I/O, L11P
1 B10 XC2S50E,
-
200E, 300E,
400E
I/O, L11N
1 A10 XC2S50E,
-
200E, 300E,
400E
I/O, VREF
1 D9 XC2S50E,
All
Bank 1, L10P
200E, 300E,
400E
I/O, L10N
1 C9 XC2S50E,
-
200E, 300E,
400E
I/O, L9P
1 B9 XC2S50E,
-
150E, 200E,
400E
I/O, L9N
1 A9 XC2S50E, XC2S400E
150E, 200E,
400E
I/O (DLL), L8P 1 A8
-
-
GCK2, I
1 B8
-
-
GCK3, I
0
I/O (DLL), L8N 0
I/O
0
I/O, L7P
0
I/O, VREF
0
Bank 0, L7N
C8
-
-
D8
-
-
A7
-
XC2S400E
E7 XC2S50E,
-
200E, 300E,
400E
D7 XC2S50E,
All
200E, 300E,
400E
70
www.xilinx.com
DS077-4 (2.3) June 18, 2008
Product Specification
 ▷