DS077 Datasheet, PDF (37/108 Pages) Xilinx, Inc – Product Availability

R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Input Switching Characteristics ⁽¹⁾
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in IOB Input Delay Adjustments for Different Standards, page 38.
Speed Grade
-7
-6
Symbol
Description
Device
Min Max Min Max Units
Propagation Delays
T_IOPI
Pad to I output, no delay
All
T_IOPID
Pad to I output, with delay
All
T_IOPLI
Pad to output IQ via transparent latch,
All
no delay
0.4
0.8
0.4
0.8 ns
0.5
1.0
0.5
1.0 ns
0.7
1.5
0.7
1.6 ns
T_IOPLID
Pad to output IQ via transparent latch, XC2S50E
1.3
3.0
1.3
3.1 ns
with delay
XC2S100E 1.3
3.0
1.3
3.1 ns
XC2S150E 1.3
3.2
1.3
3.3 ns
XC2S200E 1.3
3.2
1.3
3.3 ns
XC2S300E 1.3
3.2
1.3
3.3 ns
XC2S400E 1.4
3.2
1.4
3.4 ns
XC2S600E 1.5
3.5
1.5
3.7 ns
Sequential Delays
T_IOCKIQ
Clock CLK to output IQ
Setup/Hold Times with Respect to Clock CLK
All
0.1
0.7
0.1
0.7 ns
T_IOPICK / T_IOICKP Pad, no delay
T_IOPICKD / T_IOICKPD Pad, with delay
All
1.4 / 0
-
1.5 / 0
-
ns
XC2S50E 2.9 / 0
-
2.9 / 0
-
ns
XC2S100E 2.9 / 0
-
2.9 / 0
-
ns
XC2S150E 3.1 / 0
-
3.1 / 0
-
ns
XC2S200E 3.1 / 0
-
3.1 / 0
-
ns
XC2S300E 3.1 / 0
-
3.1 / 0
-
ns
XC2S400E 3.2 / 0
-
3.2 / 0
-
ns
XC2S600E 3.5 / 0
-
3.5 / 0
-
ns
T_IOICECK / T_IOCKICE ICE input
Set/Reset Delays
All
0.7 / 0.01 - 0.7 / 0.01 -
ns
T_IOSRCKI
SR input (IFF, synchronous)
All
0.9
-
1.0
-
ns
T_IOSRIQ
SR input to IQ (asynchronous)
All
0.5
1.2
0.5
1.4 ns
T_GSRQ
GSR to output IQ
All
3.8
8.5
3.8
9.7 ns
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
37
Product Specification