DS077 Datasheet, PDF (106/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: Pinout Tables
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Function
Bank Pin
LVDS Async.
Output Option
VREF
Option
I/O, L2N_YY
0
E5
All
-
I/O, L1P_YY
0
B4
All
-
I/O, L1N_YY
0
C4
All
-
I/O, L0P
0
A3
XC2S600E
-
I/O, L0N
0
B3
XC2S600E
-
I/O
0
A4
-
-
TCK
-
A2
-
-
FG676 Differential Clock Pins
Clock
GCK0
GCK1
GCK2
GCK3
Bank
4
5
1
0
Pin
AF14
AF13
A14
A13
P Input
Name
GCK0, I
GCK1, I
GCK2, I
GCK3, I
R
Device-Specific Pinouts
XC2S400E
XC2S600E
I/O, L2N_YY
I/O, L2N_YY
I/O, L1P_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L1N_YY
I/O
I/O, L0P_Y
-
I/O, L0N_Y
I/O
I/O
TCK
TCK
Pin
AE14
AE13
B14
B13
N Input
Name
I/O (DLL), L126P
I/O (DLL), L126N
I/O (DLL), L23P
I/O (DLL), L23N
Additional FG676 Package Pins
VCCINT Pins
H8
H19
J9
K17
L10
L17
U16
U17
V9
VCCO Bank 0 Pins
C5
C8
D11
VCCO Bank 1 Pins
C19
C22
D16
VCCO Bank 2 Pins
E24
H24
K18
VCCO Bank 3 Pins
P17
R17
T18
VCCO Bank 4 Pins
U14
U15
V16
VCCO Bank 5 Pins
U12
U13
V10
VCCO Bank 6 Pins
P10
R10
T4
VCCO Bank 7 Pins
H3
K9
L4
106
J18
T10
V18
J10
J16
L18
T23
V17
V11
T9
L9
www.xilinx.com
K10
T17
W8
J11
J17
L23
U18
AC16
AC11
U9
M10
K11
K16
U10
U11
W19
-
K12
K13
K14
K15
M17
N17
W24
AB24
AD19
AD22
AD5
AD8
W3
AB3
N10
E3
DS077-4 (2.3) June 18, 2008
Product Specification