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DS077 Datasheet, PDF (68/108 Pages) Xilinx, Inc – Product Availability
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Spartan-IIE FPGA Family: Pinout Tables
R
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L51P
4 N9 XC2S50E,
-
150E, 200E,
400E
I/O, L50N
4 T10 XC2S50E,
-
200E, 300E,
400E
I/O, VREF
4 R10 XC2S50E,
All
Bank 4, L50P
200E, 300E,
400E
I/O, L49N
4 P10 XC2S50E,
-
200E, 300E,
400E
I/O, L49P
4 R11 XC2S50E,
-
200E, 300E,
400E
I/O
4 T11
-
-
I/O, L48N
4 N10 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L48P
4 M10 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L47N
4 P11 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L47P
4 R12 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E, 400E 300E, 400E
I/O, L46N
4 T12 XC2S50E,
-
100E, 150E,
300E
I/O, L46P
4 T13 XC2S50E,
-
100E, 150E,
300E
I/O, L45N_YY 4 N11
All
-
I/O, VREF
4 M11
All
All
Bank 4,
L45P_YY
I/O, L44N_YY 4 P12
All
-
I/O, L44P_YY 4 N12
All
-
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L43N
4 R13 XC2S50E, XC2S200E,
150E 300E, 400E
I/O, L43P
4 P13 XC2S50E,
-
150E
I/O, L42N_YY 4 T14
All
-
I/O, L42P_YY 4 R14
All
-
DONE
3
PROGRAM
-
I/O (INIT),
3
L41N_YY
I/O (D7),
3
L41P_YY
I/O, L40N
3
I/O, L40P
3
I/O, L39N
3
I/O, L39P
3
I/O, VREF
3
Bank 3, L38N
I/O, L38P
3
I/O(2)
3
I/O(2)
3
I/O, L36N
3
I/O (D6), L36P 3
T15
-
-
R16
-
-
P15
All
-
P16
All
-
N15 XC2S100E,
-
150E, 400E
N16 XC2S100E, XC2S200E,
150E, 400E 300E, 400E
N14 XC2S50E,
-
100E, 150E,
200E,
300E(1)
M14 XC2S50E,
-
100E, 150E,
200E,
300E(1)
M15 XC2S50E,
All
150E, 200E,
300E, 400E
M16 XC2S50E,
-
150E, 200E,
300E, 400E
M13
-
-
L14
-
-
L15 XC2S50E, XC2S100E,
300E, 400E 150E, 200E,
300E, 400E
L16 XC2S50E,
-
300E, 400E
68
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DS077-4 (2.3) June 18, 2008
Product Specification
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