DS077 Datasheet, PDF (19/108 Pages) Xilinx, Inc – Product Availability

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Spartan-IIE FPGA Family: Functional Description
Table 8: Boundary-Scan Instructions (Continued)
Boundary-Scan Binary
Command Code[4:0]
Description
INTEST
00111
Enables boundary-scan
INTEST operation
USERCODE
01000
Enables shifting out
USER code
IDCODE
01001
Enables shifting out of
ID Code
HIGHZ
01010
Disables output pins
while enabling the
Bypass Register
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK
BYPASS
11111
Enables BYPASS
RESERVED
All other
codes
Xilinx reserved
instructions
The public boundary-scan instructions are available prior to
configuration, except for USER1 and USER2. After configu-
ration, the public instructions remain available together with
any USERCODE instructions installed during the configura-
tion. While the SAMPLE/PRELOAD and BYPASS instruc-
tions are available during configuration, it is recommended
that boundary-scan operations not be performed during this
transitional period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
To facilitate internal scan chains, the User Register provides
three outputs (Reset, Update, and Shift) that represent the
corresponding states in the boundary-scan internal state
machine.
Figure 14 is a diagram of the Spartan-IIE family boundary
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
IOB IOB IOB IOB IOB
IOB.T
DATA IN
1
0
DQ
0
sd
DQ
1
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
TDI
Bypass
Register
Instruction Register
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M _TDO
U
X
IOB.I
IOB.Q
IOB.T
1
DQ
0
1
DQ
0
1
DQ
0
sd
D
Q
LE
1
0
sd
DQ
LE
1
0
0
sd
DQ
1
LE
DS077-2 (v2.3) June 18, 2008
Product Specification
IOB.I
1
DQ
0
sd
DQ
LE
DATAOUT
SHIFT/ CLOCK DATA
CAPTURE REGISTER
UPDATE
Figure 14: Spartan-IIE Family Boundary Scan Logic
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1
0
EXTEST
DS001_09_032300
19