DS077 Datasheet, PDF (43/108 Pages) Xilinx, Inc – Product Availability

R
Spartan-IIE FPGA Family: DC and Switching Characteristics
DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
Symbol
F_CLKINHF
F_CLKINLF
T_DLLPW
Description
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width
worst-case values across the recommended operating con-
ditions.
F_CLKIN
-
-
≥25 MHz
≥50 MHz
≥100 MHz
≥150 MHz
≥200 MHz
≥250 MHz
≥300 MHz
Speed Grade
-7
-6
Min Max Min Max
60
320
60
275
25
160
25
135
5.0
-
5.0
-
3.0
-
3.0
-
2.4
-
2.4
-
2.0
-
2.0
-
1.8
-
1.8
-
1.5
-
1.5
-
1.3
-
NA
-
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 22, page 44, provides definitions for various parame-
ters in the table below.
CLKDLLHF CLKDLL
Symbol
T_IPTOL
T_IJITCC
T_LOCK
Description
Input clock period tolerance
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock⁽¹⁾
F_CLKIN
> 60 MHz
50-60 MHz
Min Max Min Max Units
-
1.0
-
1.0
ns
- ±150 - ±300 ps
-
20
-
20
μs
-
-
-
25
μs
40-50 MHz
-
-
-
50
μs
30-40 MHz
-
-
-
90
μs
25-30 MHz
-
-
-
120
μs
T_OJITCC
T_PHIO
T_PHOO
T_PHIOM
T_PHOOM
Output jitter (cycle-to-cycle) for any DLL clock output⁽²⁾
Phase offset between CLKIN and CLKO⁽³⁾
Phase offset between clock outputs on the DLL⁽⁴⁾
Phase difference between CLKIN and CLKO⁽⁵⁾
Phase difference between clock outputs on the DLL⁽⁶⁾
-
± 60
-
± 60
ps
- ±100 - ±100 ps
- ±140 - ±140 ps
- ±160 - ±160 ps
- ±200 - ±200 ps
Notes:
1. Commercial operating conditions. Add 30% for Industrial operating conditions.
2. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
3. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
4. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
5. Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
6. Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
43
Product Specification